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Nehalem is the codename for an Intel processor microarchitecture, which is the successor to the older Core microarchitecture. A preview system with two Nehalem processors was shown at Intel Developer Forum in 2007, and the first processor released with the Nehalem architecture was the desktop Core i7, which was released in November 2008. The first generation of the Intel Core series of processors, Nehalem designs led to the introduction of Core i7 and i5 models (no Core i3 is based on Nehalem). The subsequent Westmere and Sandy Bridge designs would include Core i3 processors. "Nehalem" is a recycled Intel codename and namesake of the Nehalem River. It is an architecture that differs radically from Netburst, while retaining some of the latter's minor features. Nehalem-based microprocessors use the 45 nm process, run at higher clock speeds, and are more energy-efficient than Penryn microprocessors. Hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores. Nehalem was replaced with the Sandy Bridge microarchitecture, released in January 2011. ==Technology== * Hyper-threading reintroduced. * Intel Turbo Boost 1.0.〔http://files.shareholder.com/downloads/INTC/0x0x348508/C9259E98-BE06-42C8-A433-E28F64CB8EF2/TurboBoostWhitePaper.pdf〕 * 4–12 MB L3 cache * Second-level branch predictor and translation lookaside buffer * Native (all processor cores on a single die) quad- and octa-core processors * Intel QuickPath Interconnect in high-end models replacing the legacy front side bus * 64 KB L1 cache per core (32 KB L1 data and 32 KB L1 instruction), and 256 KB L2 cache per core. * Integration of PCI Express and DMI into the processor in mid-range models, replacing the northbridge * Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM2 channels * Second-generation Intel Virtualization Technology, which introduced Extended Page Table support, virtual processor identifiers (VPIDs), and non-maskable interrupt-window exiting 〔(【引用サイトリンク】title=Inside Nehalem: Intel's Future Processor and System )〕 * SSE4.2 and POPCNT instructions * Macro-op fusion now works in 64-bit mode. * 20 to 24 pipeline stages〔(【引用サイトリンク】title=Feature - Intel Core i7 - Nehalem Architecture Dive )〕 : 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Nehalem (microarchitecture)」の詳細全文を読む スポンサード リンク
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